This invention relates to a method of fabricating a storage capacitor for a DRAM memory cell, in particular a capacitor of stacked fin structure.
In a DRAM cell, it is desirable to reduce the size of a memory cell for increasing the memory capacity of an integrated circuit (IC). Yet, the storage capacitance of the cell should be made large to increase charge storage. The requirements for small size and large storage capacitance are inconsistent.
To overcome this problem, a stacked capacitor of fin structure has been disclosed in U.S. Pat. Nos. 5,290,726 and 5,128,273. By stacking a number of fins as the electrode of the storage capacitor, the effective area of the electrode, hence the capacitance per cell, is greatly increased.
In all the previous methods of fabrication, they all require more than three masking steps. It is desirable to reduce the number of masking steps in fabricating an IC to lower cost and increase yield.